The present invention relates to a semiconductor structure, and more specifically, to a vertical through silicon via (TSV) for providing vertical interconnection in a semiconductor structure.
In electronics, a through-silicon via (TSV) is a vertical electrical connection that passes through a silicon wafer, for example. TSV technology is important in creating 3D packages and 3D integrated circuits. A 3D package contains two or more chips (i.e., integrated circuits) stacked vertically. In some 3D packages, TSVs replace edge wiring by creating vertical connections through the body of the chips, for example. Conventionally, the vertical through-via has been considered an impediment to high speed signals rather than as an asset. Further, the vertical interconnect is not used in a manner which enhances signal transfer or power supply distribution.